1. Field of the Invention
The present invention relates to a method of fabricating openings and plugs. More particularly, the present invention relates to a method of manufacturing openings and plugs for effectively suppressing outgasing of dielectric material.
2. Description of the Related Art
When the Ultra Large Scale Integration technology is mature to be able to manufacture the line width below 0.13 micro meter, in order to increase the processing speed of the chip, it is necessary to overcome the delay due to impedance and capacitance. Therefore, copper and the dielectric material with relatively low dielectric constant are used to form the interconnecting structure. However, because of the relatively worse physical properties, such as relatively soft, relatively thermal unstable, relatively hard to manufacture and relatively easy to run off the composition element (the so-called outgasing phenomenon), of the dielectric material with relatively low dielectric constant, it is difficult to maintain good-defect control in copper/low dielectric material process.
FIGS. 1A through 1C are schematic cross-sectional views showing the conventional progression of manufacturing steps for producing an opening for dual damascene structure.
As shown in FIG. 1A, a dielectric layer 104 is formed over a substrate 100 partially covered by a conductive layer 102. The dielectric layer 104 is made from dielectric material with relatively low dielectric constant. A patterned photoresist layer 106 is formed on the dielectric layer 104 and exposes portion of the dielectric layer 104.
Referring to FIG. 1B, a portion of the dielectric layer 104 is removed by using photoresist layer 106 (as shown in FIG. 1A) as a mask until the conductive layer 102 is exposed to form a via 108 in a dielectric layer 104a. The photoresist layer 106 is removed. A patterned photoresist layer 110 is formed over the substrate 100.
As shown in FIG. 1C, a portion of the dielectric layer 104a is removed to form a via 108a and a trench 112 in a dielectric layer 104b by using the patterned photoresist layer 110 (as shown in FIG. 1B) as a mask. The via 108a and the trench 112 are composed to form a dual damascene opening 114. The photoresist layer 110 is removed.
In the process described above, the dielectric layer 104 itself has outgasing phenomenon, that is the component of the dielectric layer 104 running off. Therefore, the portion of the photoresist layers in touch with the dielectric layer 104 will react with the running-off dielectric component and the latter development process on the photoresist layers will happen to be incomplete. Hence, the definition for forming via and trench will be inaccuracy. Furthermore, in the latter manufacturing procedure, in order to prevent the filling metal in opening from spike phenomenon, electromigration or poor adhesion, a block layer is formed in the opening to be a protection. Nevertheless, defects will be formed in the block layer since the outgasing of the dielectric layer with relatively low dielectric constant and then the reliability of the device is decreased.
There is a well known method for improving the outgasing phenomenon of the dielectric layer with relatively low dielectric constant, that is forming a block layer on the dielectric layer. However, this kind of method will lead to higher manufacturing cost and producing extra stress to induce further defects. Additionally, because of the existence of the block layer, it is easy to induce parasitic capacitors, especially when the block layer is formed by dielectric layer with relatively high dielectric constant.